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| december 2002 as7c33128ntd32a as7c33128ntd36a tm ! features ? organization: 131,072 words 32 or 36 bits ntd ?1 architecture for effi cient bus operation fast clock speeds to 166 mhz in lvttl/lvcmos fast clock to data access: 3.5/4.0/5.0 ns fast oe access time: 3.5/4.0/5.0 ns fully synchronous operation flow-through or pipelined mode asynchronous output enable control 1. ntd ? is a trademark of alliance semiconductor corporation. economical 100-pin tqfp package byte write enables clock enable for operation hold multiple chip enable s for easy expansion 3.3v core power supply 2.5v or 3.3v i/o operation with separate v ddq 30 mw typical standby power self-timed write cycles interleaved or linear burst modes snooze mode for standby operation write data registers address d q clk register output register dq [a:d] 17 17 clk ce0 ce1 ce2 a[16:0] oe clk cen control clk logic data d q clk input register 32/36 oe 128k x 32/36 sram array r/w dq [a:d ] bwa bwc bwb bwd clk q d ft adv / ld lbo burst logic addr. registers write delay 17 zz clk 17 17 32/36 32/36 32/36 32/36 32/36 logic block diagram note: pins 1,30,51,80 are nc for 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 lbo a a a a a1 a0 nc nc v ss v dd nc nc a a a a a a 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 a a ce0 ce1 bwd bwc bwb bwa ce2 v dd v ss clk r/w cen oe adv/ld nc nc a a tqfp 14x20mm a dqpc, nc dqc dqc v ddq v ssq dqc dqc dqc dqc v ssq v ddq dqc dqc ft v dd v dd v ss dqd dqd v ddq v ssq dqd dqd dqd dqd v ssq v ddq dqd dqd dqpd, nc dqpb, nc dqb dqb v ddq v ssq dqb dqb dqb dqb v ssq v ddq dqb dqb v ss zz dqa dqa v ddq v ssq dqa dqa dqa dqa v ssq v ddq dqa dqa dqpa, nc v dd v dd pin arrangement f or tqfp (top view) selection guide -166 -133 -100 units minimum cycle time 6 7.5 10 ns maximum pipelined clock frequency 166 133 100 mhz maximum pipelined clock access time 3.5 4 5 ns maximum operating current 475 425 325 ma maximum standby current 130 100 90 ma maximum cmos standby current (dc) 30 30 30 ma !""#$%&" !""#$%&"' ! functional description the as7c33128ntd36a family is a high performance cmos 4-mbit sync hronous static random access me mory (sram) device organized as 131,072 words 32 or 36 bits that incorporates a late late write. this variation of the 4mb sychronous sram uses the no turnaro und delay (ntd) architecture, featuring an enhanced write operatio n that improves bandwidth over pipelined burst devices. in a normal pipelined burst device, the write data, command, and address are a ll applied to the device on the same clock edge. if a read command follows thi s write command, the system must wait for two dead cycles for v alid data to become available. these dead cycles can significantly reduce ov erall bandwidth for applications requiring random access or read -modify-write operations. ntd devices use the memory bus more efficiently by introducing a write latency that matches the two-cycle pipelined or one-cycl e flow- through read latency. write data is applied two cycles after the write command and addr ess, allowing the read pipeline to clear . with ntd, write and read operations can be used in any order without producing dead bus cycles. assert r/w low to perform write cycles. byte write en able controls write access to specific bytes, or can be tied low for full 32/36 bit writes. write enable signals, along with the write a ddress, are registered on a rising edge of the clock. write data is applied to the device two clock cycles later. unlike some asynchronous srams, output enable oe does not need to be toggled for write operations. it can be tied low for normal operations. outputs go to a high im pedance state when the device is deselected by any of the three chip enable inputs. ( refer to synchronous truth table on page 4.) in pipelined mode, a two-cycle deselect latency allows pending read or write operations to be completed. use the adv/ld (burst advance) input to perform burst read, write, and deselect operations. when adv/ld is high, external addresses, chip select, and r/w pins are ignored, and internal address counters in crement in the count sequence specified by the lbo control. any device operations, including burst, can be stal led using the clock enable input, cen = 1. the as7c33128ntd36a and as7c33128ntd32a operate with a 3.3v 5% power supply for the device core (v dd ). dq circuits use a separate power supply (v ddq ) that operates across 3.3v or 2.5v ranges. these devices are available in a 100-pin 1420 mm tqfp package. capacitance parameter symbol signals test conditions max unit input capacitance c in address and control pins v in = 0v 5 pf i/o capacitance c i/o i/o pins v in = v out = 0v 7 pf burst order interleaved burst order lbo = 1 linear burst order lbo = 0 starting address 00 01 10 11 starting address 00 01 10 11 first increment 01 00 11 10 first increment 01 00 11 10 second increment 10 11 00 01 second increment 10 11 00 01 third increment 11 10 01 10 third increment 11 10 01 10 !""#$%&" !""#$%&"' ! " stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. exposure to abso lute maximum rating conditions may affect reliability. signal descriptions signal i/o properties description clk i clock clock. all inputs except oe , ft , lbo , and zz are synchronous to this clock. cen i sync clock enable. when de-asserted high, the clock input signal is masked. a, a0, a1 i sync address. sampled when a ll chip enables are active and adv/ld is asserted. dq[a,b,c,d] i/o sync data. driven as output when the chip is enabled and oe is active. ce0 , ce1, ce2 isync synchronous chip enables. sampled at the rising edge of clk, when adv/ld is asserted. are ignored when adv/ld is high. adv/ld isync advance or load. when sampled high, the intern al burst address counter will increment in the order defined by the lbo input value. (refer to table on page 2) when low, a new address is loaded. r/w isync a high during load initiates a read opera tion. a low during load initiates a write operation. is ignored when adv/ld is high. bw[a,b,c,d] isync byte write enables. used to control write on individual bytes. sampled along with write command and burst write. oe i async asynchronous output enable. i/o pins are not driven when oe is inactive. lbo istatic count mode. when driven high, count sequ ence follows intel xor convention. when driven low, count sequence follows linear conv ention. this input should be static when the device is in operation. ft istatic flow-through mode.when low, enables single register flow-through mode. connect to v dd if unused or for pipelined operation. zz i async snooze. places device in low power mode . data is retained. connect to vss if unused. nc - - no connects. note that pin 83 & 84 will be used for future address expansion to 8 mb and16mb density. absolute maximum ratings parameter symbol min max unit power supply voltage relative to vss v dd , v ddq ?0.5 +4.6 v input voltage relative to vss (input pins) v in ?0.5 v dd + 0.5 v input voltage relative to vss (i/o pins) v in ?0.5 v ddq + 0.5 v power dissipation p d ?1.8w dc output current i out ?50ma storage temperature (plastic) t stg ?65 +150 o c temperature under bias (junction) t bias ?65 +135 o c !""#$%&" !""#$%&"' ! key: x = don?t care, l = low, h = high. 1. should be low for burst write, unles s specific bytes need to be inhibited. 2. refer to state diagram below. synchronous truth table ce0 ce1 ce2 adv/ ld r/w bw[a:d] oe cen address source clk operation h x x l x x x l na l to h deselect, high-z x l x l x x x l na l to h deselect, high-z x x h l x x x l na l to h deselect, high-z l h l l h x x l external l to h begin read l h l l l l x l external l to h begin write xxxhxx 1 x l burst counter l to h burst 2 x x x x x x x h stall l to h inhibit the clk tqfp thermal resistance description conditions symbol ty p i c a l units thermal resistance (junction to ambient) 1 % test conditions follow standard test methods and procedures for measuring thermal impedance, per eia/jesd51. ja 40 c/w thermal resistance (junction to top of case) 1 jc 8c/w dsel dsel read read burst burst write read write burst read read write d s e l r e a d burst write dsel d s e l w r i t e w r it e burst dsel burst burst write read & $%& ( ) !""#$%&" !""#$%&"' ! * recommended operating conditions parameter symbol min nominal max unit supply voltage v dd 3.135 3.3 3.465 v vss 0.0 0.0 0.0 v 3.3v i/o supply voltage v ddq 3.135 3.3 3.465 v vssq 0.0 0.0 0.0 2.5v i/o supply voltage v ddq 2.35 2.5 2.65 v vssq 0.0 0.0 0.0 input voltages 1 1 input voltage ranges apply to 3.3v i/o operation. for 2.5v operation, contact factory for input specifications. address and control pins v ih 2.0 ? v dd + 0.3 v v il ?0.5 2 2 v il min. = ?2.0v for pulse width less than 0.2 x t rc . ?0.8v i/o pins v ih 2.0 ? v ddq + 0.3 v v il -0.5 2 ?0.8 ambient operating temperature t a 0?70c dc electrical characteristics for 3.3v i/o operation parameter sym test conditions 166 133 100 unit min max min max min max input leakage current 1 1 lbo pin has an internal pull-up, and input leakage = 10 a. note: icc given with no output loading. icc increases with faster cycle times and greater output loading. | i li | v dd = max, v in = vss to v dd ?2?2?2a output leakage current | i lo | oe v ih, v dd = max, v out = vss to v dd ?2?2?2a operating power supply current i cc ce = v il , ce = v ih , ce = v il , f = f max, i out = 0 ma ? 475 ? 425 ? 325 ma standby power supply current i sb deselected, f = f max ? 130 ? 100 ? 90 ma i sb1 deselected, f = 0 , all v in 0.2v or v dd - 0.2v ?30?30?30ma i sb2 deselected, f=f max , zz v dd - 0.2v all v in v il or v ih ?30?30?30ma output voltage v ol i ol = 8 ma, v ddq = 3.6v ? 0.4 ? 0.4 ? 0.4 v v oh i oh = ?4 ma, v ddq = 3.0v 2.4 ? 2.4 ? 2.4 ? v !""#$%&" !""#$%&"' ! ' see ?notes? on page 9. dc electrical characterist ics for 2.5v i/o operation parameter sym test conditions 166 133 100 unit min max min max min max output leakage current | i lo | oe v ih, v dd = max, v out = vss to v dd -11-11-11a output voltage v ol i ol = 2 ma, v ddq = 2.65v ? 0.7 ? 0.7 ? 0.7 v v oh i oh = ?2 ma, v ddq = 2.35v 1.7 ? 1.7 ? 1.7 ? timing characteristics over operating range parameter sym 166 133 100 unit notes min max min max min max clock frequency f max - 166 - 133 - 100 mhz cycle time (pipelined mode) t cyc 6 - 7.5 - 10 - ns cycle time (flow-through mode) t cycf 10 - 12 - 12 - ns clock access time (pipelined mode) t cd -3.5-4.0-5.0ns clock access time (flow-through mode) t cdf -9-10-12ns output enable low to data valid t oe -3.5-4.0-5.0ns clock high to output low z t lzc 0-0-0-ns2,3,4 data output invalid from clock high t oh 1.5 - 1.5 - 1.5 - ns 4 output enable low to output low z t lzoe 0-0-0-ns2,3,4 output enable high to output high z t hzoe -3.5-4.0-4.5ns2,3,4 clock high to output high z t hzc -3.5-4.0-4.5ns2,3,4 clock high to output high z t hzcn -1.5-2.0-2.5ns5 clock high pulse width t ch 2.4 - 2.5 - 3.0 - ns 6 clock low pulse width t cl 2.2 - 2.5 - 3.0 - ns 6 address setup to clock high t as 1.5 - 1.5 - 2.0 - ns 7 data setup to clock high t ds 1.5 - 1.5 - 2.0 - ns 7 write setup to clock high t ws 1.5 - 1.5 - 2.0 - ns 7 chip select setup to clock high t css 1.5 - 1.5 - 2.0 - ns 7 clock enable setup to clock high t cens 1.5 - 1.5 - 2.0 - ns 7 adv/ld setup to clock high t advs 1.5 - 1.5 - 2.0 - ns 7 address hold from clock high t ah 0.5 - 0.5 - 0.5 - ns 7 data hold from clock high t dh 0.5 - 0.5 - 0.5 - ns 7 write hold from clock high t wh 0.5 - 0.5 - 0.5 - ns 7 adv/ld hold from clock high t advh 0.5 - 0.5 - 0.5 - ns 7 clock enable hold from clock high t cenh 0.5 - 0.5 - 0.5 - ns 7 output rise time (0 pf load) t r 1.5 - 1.5 - 1.5 - v/ns output fall time (0 pf load) t f 1.5 - 1.5 - 1.5 - v/ns !""#$%&" !""#$%&"' ! ! timing waveform of read/write cycle note: y = xor when lbo = high/no connect. y = add when lbo = low. bw[a:b] is don?t care. + , - .$ /+ /. -0 .$ . . &1-& (2 &&(. &3 /. +4/. 52 " * ' &6 7 &6 *7 36 '7 &6 7 &6 y 7 36 "7 36 7 36 y 7 .$+ & &+ -4 & +4 -4/. burst write d(a2 1) read q(a3) read q(a4) burst read q(a4 1) write d(a5) read q(a6) write d(a7) dsel write d(a1) write d(a2) &1+ 2 2+ 2 2+ t + t as t ah &3 &6 7 &6 *7 36 '7 &6 7 &6 y0 7 36 "7 36 7 36 y 7 89 . &1 &6 %7 y y !""#$%&" !""#$%&"' ! # $/ notes: oe is low. y = xor when lbo = high/no connect. y = add when lbo = low -0 .$ . . &1-& (2 &&(. &3 52 36 7 &6 7 36 y0 7 36 y 7 burst q(a1 01) stall dsel burst dsel write d(a2) burst nop d(a2 01) write nop d(a3) " &3 36 7 &6 7 y 36 y 7 read q(a1) burst q(a1 10) burst d(a2 10) . 8 &6 y 7 y y y y !""#$%&" !""#$%&"' ! : ac test conditions z 0 =50 ? d out 50 ? v l =1.5v figure b: output load (a) 30 pf* figure a: input waveform 10% 90% vss 90% 10% +3.0v output load: for t lzc , t lzoe , t hzoe , t hzc, see figure c. for all others, see figure b. input pulse level: vss to 3v. see figure a. input rise and fall time (measured at 0.3v and 2.7v): 2 ns. see figure a. input and output timing reference levels: 1.5v. 353 ? / 1538? 5 pf* 319 ? / 1667? d out gnd figure c: output load (b) *including scope and jig capacitance thevenin equivalent: +3.3v for 3.3v i/o, +2.5v for 2.5v i/o notes package dimensions 100-pin quad flat pack (tqfp) tqfp min max a1 0.05 0.15 a2 1.35 1.45 b 0.22 0.38 c 0.09 0.20 d 13.90 14.10 e 19.90 20.10 e 0.65 nominal hd 15.90 16.10 he 21.90 22.10 l 0.45 0.75 l1 1.00 nominal 0 7 dimensions in millimeters he e hd d b e a1 a2 l1 l c 1 for test conditions, see ac test conditions , figures a, b, and c. 2 this parameter measured with output load condition in figure c 3 this parameter is sampled and not 100% tested. 4t hzoe is less than t lzoe , and t hzc is less than t lzc at any given temperature and voltage. 5 t hzcn is a no-load parameter to indicate exactly when sram outputs have stopped driving. 6t ch measured as high above vih, and t cl measured as low below vil 7 this is a synchronous device. all addr esses must meet the specified setup and hold times for all rising edges of clk. all other synchronous inputs must meet the setup and hold times with stable logic levels for all rising edges of clk when chip is enabled. ? copyright alliance semiconductor corporat ion. all rights reserved. our three-point logo, our name and intelliwatt are tradema rks or registered trademarks of alliance. all other brand and pr oduct names may be the trademarks of their respective companies. alliance reserves the right to make changes to this document and its products at any time without notice. alliance assumes no responsib ility for any errors that may appear in this document. the data contained here in represents alliance?s best data and/or estima tes at the time of issuance. alliance reserves the right to change or correct this data at a ny time, without notice. if the product described herein is under development, significant changes to these specifications are possible. the information in this product data sheet is i ntended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any us er or customer. alliance does not assume any responsibility or l iability arising out of the application or use of any product described he rein, and disclaims any express or implied warranties related to th e sale and/or use of alliance products in cluding liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in alliance?s terms and conditions of sale (which are available fro m alliance). all sales of allian ce products are made exclusively according to alliance?s terms and conditions of sale. the purchase of products from alliance does not convey a license under any patent rights, copyrights, mask works rights, trademarks , or any other intellectual propert y rights of alliance or third parties. alliance does not authorize its products for use as critical components in life-supporting sy stems where a malfunction or fail ure may reasonably be expecte d to result in significant injury to the user, and the inclusion of alliance products in such life- supporting systems implies that the manufacture r assumes all risk of such use and agrees to indemnify alliance against all clai ms arising from such use. as7c33128ntd32a as7c33128ntd36a ! 1.alliance semiconductor sram prefix 2.operating voltage: 33 = 3.3v 3.organization: 128 = 128 k 4.ntd = no turnaround delay 5.organization: 32 = x32, 36 = x36 6.production version: a = first production version 7.clock speed (mhz) 8.package type: tq = tqfp 9.operating temperature: c = commercial ( 0 c to 70 c), i = industrial ( -40 c to 85 c) ordering information package width 166 mhz 133 mhz 100 mhz tqfp 32 as7c33128ntd32a-166tqc as7c33 128ntd32a-133tqc as7c33128ntd32a-100tqc tqfp 36 as7c33128ntd36a-166tqc as7c33 128ntd36a-133tqc as7c33128ntd36a-100tqc fbga 32 as7c33128ntd32a-166bc as7c33128ntd32a-133bc as7c33128ntd32a-100bc fbga 36 as7c33128ntd36a-166bc as7c33128ntd36a-133bc AS7C33128NTD36A-100BC part numbering guide as7c 33 128 ntd 32/36 a ?xxx tq c/i 1 23 45678 9 |
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